The process for forming a field effect transistor on the surface of a semiconductor substrate is typically performed as follows. For instance, before forming a gate electrode, impurity is injected into the semiconductor substrate to form a well region of the field effect transistor. In the well region, an implant region for adjusting the threshold voltage (Vt) is further formed. Next, after forming a gate electrode, impurity is injected to form a lightly doped region (lightly doped drain, LDD), a source region, and a drain region (see, e.g., JP-A-2004-228592).
In the manufacturing steps for the respective regions, photolithography is performed typically for each step. Furthermore, heat treatment for diffusing and activating the impurity is also performed for each step. In such manufacturing steps, the number of manufacturing steps cannot be reduced. Furthermore, the impurity concentration distribution in the well region immediately below the gate electrode cannot be sufficiently controlled. Unfortunately, this increases the cost of manufacturing a semiconductor device including a field effect transistor. Furthermore, the short channel effect of the field effect transistor cannot be suppressed.